(1) Field of the Invention
The invention relates to a method of forming gates, resistors, and capacitors in the fabrication of integrated circuits, and more particularly, to a method of forming gates, resistors, and capacitors having different polysilicon resistances in the manufacture of integrated circuits.
(2) Description of the Prior Art
In order to form different polysilicon resistances for the gate, resistor, and capacitor plate in an integrated circuit, the area and length of the polysilicon must be modified to meet the different criteria. This is a complex process that will increase the cost of manufacturing. Related process issues such as lateral diffusion are also a concern.
Co-pending U.S. patent application Ser. No. 09/073,948 (TSMC-97-515) to Chen et al, filed on May 7, 1998, teaches patterning a polysilicon layer to form different thicknesses of polysilicon and then doping the polysilicon to form resistors having different resistances. Co-pending U.S. patent application Ser. No. 09/073,950 (TSMC-97-508) to Shen et al, filed on May 7, 1998, teaches forming different thicknesses of an oxide layer over a polysilicon layer and then doping the polysilicon through the different oxide thicknesses to form resistors having different resistances. U.S. Pat. No. 5,554,554 to Bastani et al teaches forming high and low resistance poly loads by a selective ion implantation process. U.S. Pat. No. 5,705,418 to Liu shows a method of forming high-resistance load resistors by using a LOCOS process to reduce the thickness of portions of a polysilicon layer. U.S. Pat. No. 5,514,617 to Liu and U.S. Pat. No. 5,554,873 to Erdeljac et al teach selective a doping to form variable resistance polysilicon. U.S. Pat. No. 4,643,777 to Maeda shows selective ion implantation to form low resistance polysilicon regions. U.S. Pat. No. 5,662,884 to Liu discloses a high resistance poly load resistor. U.S. Pat. No. 5,474,948 to Yamazaki discloses a poly load resistor.